The invention relates to apparatus and methods for converting digital words into corresponding analog output signals, especially to circuits and methods for minimizing non-linearity in such analog output signals due to variations in voltages across ground conductor resistances, which variations are caused by changes in the digital words.
Monolithic digital to analog converter circuits are well known in the art and typically include a plurality of bit switches, each responsive to a particular bit within an input digital word to selectively steer an associated "bit switch current" to a summing node in a resistor ladder network in order to make a contribution to an analog output current. The resistive ladder networks usually "scale" contributions of the various bit switch currents in a binarily weighted fashion when the corresponding bit switches are "on", i.e., "active". The contribution of each active bit switch current is progressively halved, starting with the most significant bit switch and moving toward the least significant "active" bit switch. In a typical prior art structure, the resistor network is an "R/2R network" in which a first thin, aluminum metalization line (referred to herein as a ground conductor) conducts a ground current to one end of half of the resistors, the other end of each of those resistors being connected to the collector of a respective NPN "bit switch transistor" (also referred to herein as a "bit current transistor"). The distributed resistance of the ground conductor is very small compared to the resistance of the ladder network resistors, but nevertheless is finite. The other resistors of the R/2R network are connected between respective pairs of adjacent bit switch transistors. Each of the bit switch transistors is paired in a common emitter configuration with a corresponding "waste current transistor", the collector of which is connected to a second common ground current conductor referred to herein as a "waste current conductor". Thus, if a particular bit is "active", the corresponding bit current is switched through the resistive ladder network, and a portion of that bit current flows through the distributed resistance of the first ground conductor. However, if that bit is "inactive" or off, then the entire bit switch current (now referred to as the "waste current" for that bit) is steered through the corresponding waste current transistor and into the waste current ground conductor. In this event, none of the bit switch current flows through the distributed resistance of the first ground conductor.
If the distributed resistance of the first ground conductor is appreciable, the variation in voltage across the resistance of the first ground conductor (as various bits are switched on or off) causes errors that are referred to as "non-linearity" errors. (Non-linearity errors can be graphically represented by the deviation from a straight line of the average of the value of the analog output current plotted versus the numerical value of the digital input word).
Those skilled in the art have long been aware of the existence of non-linearity errors caused by bit current switching. The non-linearity errors are due to the above-mentioned variation in voltage drops across the distributed resistance of the first ground conductor and various other causes, including self heating of resistors and thermal interaction between devices in the chip. The portion of the non-linearity due to inaccurate splitting of the various bit currents switched into the ladder network can be compensated, for example, by state-of-the art laser trimming techniques, to adjust the values of the ladder network resistors (which are usually composed of nichrome). However, the portion of the non-linearity errors due to the above-mentioned voltage variations across the distributed resistance of the first ground conductor cannot be eliminated by trimming of the ladder network resistors. To the extent that past attempts have been made to reduce such voltage variations, the reductions have been accomplished by simply making the first ground conductor metal line wider, thereby reducing its resistance. Typically, the resistance of integrated circuit metal conductors may be only approximately 0.026 ohms per square, whereas the ladder resistors may vary from 100 ohms for a high speed digital to analog converter to several thousand ohms per square for a slow speed digital to analog converter. For digital to analog converters with eight-bit accuracy, the non-linearities due to resistance of the first ground conductor generally have been sufficiently narrow that they have been ignored. However, for higher accuracy digital to analog converters, such as a twelve bit digital to analog converters, the linearity errors caused by the voltage variations (due to bit pattern switching) across the distributed resistance of the first metal conductor can be a very significant source of non-linearity errors. To our knowledge, no one has previously suggested a practical solution (other than simply expanding the width of the first ground conductor) for reducing non-linearity errors caused by voltage drops across the first ground conductor, which voltage drops are caused by variations in the input word.
The integrated circuit layout structure of prior art digital to analog converter circuits generally includes a resistive ladder network positioned on a portion of the integrated circuit surface. The bit switch current transistors are respectively formed in separate electrically isolated N type regions adjacent to the resistor ladder nodes into which the respective bit currents are to be switched when the various bits are active. The waste current transistors typically are all disposed in a single, elongated isolated N type region located on the side of the bit switch transistors opposite to the resistor ladder. This can be done since all of the collectors of the waste current transistors are connected to the same waste current conductor. Portions along the entire length of this common collector region are shorted to the metal waste current conductor, which is connected to a main ground voltage conductor (such as bonding pad) on the integrated circuit substrate. This is a very efficient topography.
Those skilled in the art know that the yield, and hence the cost of an integrated circuit is highly dependent upon the chip size. The above described layout structure, with all of the waste current transistors sharing only a single isolated N type region, is very efficient in use of chip area. Therefore, the technique of minimizing the above-mentioned bit pattern variations in the voltage drop across the first conductor resistance by simply widening the first conductor to reduce its resistance would generally be thought by those skilled in the art to be more desireable than making changes in circuitry if such changes which would require each of the waste current transistors to be formed in a separate isolated N type region.
Nevertheless, we have found that as the complexity and required accuracy of a digital to analog converter circuit increases, adequately increasing the width of the first metal conductor to reduce non-linearity errors due to waste current switching to provide sufficient accuracy may excessively increase the amount of chip area required.
Therefore, it is an object of the invention to provide a circuit and method for reducing bit-pattern-sensitive non-linearities caused by distributed resistance of a ground voltage conductor in a resistive ladder of a digital to analog converter circuit.